In recent years, in information processing apparatuses such as servers and computers, the performance (particularly bandwidth) of components such as a CPU (Central Processing Unit) and so on has greatly improved. In order to increase the total bandwidth of the entire information processing apparatus, it is often required to increase the speed of a transmission/reception circuit for transmitting and receiving data between chips such as CPUs, between a plurality of elements in a chip, or between a plurality of circuit blocks. In addition, it is often required to speed up the transmission/reception circuit for transmitting and receiving data between boards and between housings. In a transmission/reception circuit requiring high-speed data communication by electric communication or optical communication as described above, for example, a signal equalizer (equalizer) is used to compensate for deterioration of a data signal generated in a communication path.
One example of the equalizer is a decision feedback equalizer (DFE) (see, e.g., Non-Patent Document 1). The DFE is a circuit for compensating for signal deterioration due to inter-symbol interference (ISI) by subtracting the ISI from an input signal, which is input to a comparator in the state in which the ISI is superimposed thereon, by changing a decision threshold of the comparator. In order to compensate for the input data signal every bit, the DFE changes the decision threshold of the comparator every UI (unit-interval)) of a data width of 1 bit.
On the other hand, in recent years, in lieu of a transmission scheme based on binary modulation such as NRZ (Non Return to Zero), a standard for data communication based on quaternary pulse amplitude modulation (PAM) has been formulized. Hereinafter, the quaternary pulse amplitude modulation is sometimes referred to as “PAM4” and a quaternary pulse amplitude modulation signal is sometimes referred to as a “PAM4 signal”. As a DFE for PAM4, there has been proposed a speculative DFE that feeds back a 2-bit output result output from a PAM4 decoder (see, e.g., Non-Patent Document 2).
Related techniques are disclosed in, for example, Japanese Laid-Open Patent Publication No. 2009-231954.
Related techniques are disclosed in, for example, Sam Palermo, ECEN689: Special Topics in High-Speed Links Circuits and Systems, Spring 2010, Class Notes Lecture 19, Texas A&M University (Non-Patent Document 1), Peter Park, “A 4PAM/2PAM coaxial cable receiver analog front-end targeting 40 Gb/s in 90-nm CMOS” (Non-Patent Document 2) and T. Shibasaki, et al., “A 56-Gb/s Receiver Front-End with a CTLE and 1-Tap DFE in 20-nm CMOS”, IEEE Symp. VLSI Circuits, pp. 112-113, June 2014 (Non-Patent Document 3).